(1) Field of the Invention
The invention relates to digital memory devices and, more particularly, to a highly-integrated, Flash memory and mask ROM array architecture.
(2) Description of the Prior Art
Flash memory is widely used in today's electronic products, especially for portable applications that require non-volatility and in-system re-programmability. The basic Flash memory cell structure consists of a control gate, a floating gate, source, and drain. The source and drain are two heavily doped regions on a silicon substrate. A channel exists for electrons to flow from drain to source. The floating gate is located between the control gate and channel. The floating gate electrode is isolated from the substrate by a thin tunnel oxide layer. A dielectric layer isolates the floating gate electrode from the control gate electrode.
When the control gate, drain, and source are biased to proper voltages, electrons can move through the tunneling oxide to either charge or discharge the floating gate. These bias conditions are called programming and erasing operations. By isolating the floating gate electrode, electrons on the floating gate are trapped during normal, non-program and non-erase, operating conditions. If the program or erase operations cause electron movement between the channel region and the floating gate, then this is considered a “channel operation.” If the program or erase operations cause electron movement between the edge of either the source or drain regions and the floating gate, then this is considered an “edge operation.”
An increase in the number of electrons on the floating gate will cause the cell threshold voltage to increase. The threshold voltage is defined as the control gate bias needed to allow current flow from drain to source. The threshold voltage depends on the amount of charge trapped in the floating gate. Therefore, the Flash cell can be programmed or erased by either injecting electrons into or removing electrons from the floating gate. Single level cell (SLC) technology requires two different threshold voltages to represent a “0” or a “1.” Multiple level cell (MLC) technology uses N threshold voltages to represent 2N possible values per cell.
Two different operations are used to change the Flash memory cell threshold voltage. An erase operation, that is typically applied to a large number of cells, called a block, will collectively change the threshold voltage for all the cells in the block. The program operation is performed on a smaller number of cells, called a page. During programming, the threshold voltage of each cell is changed selectively depending on the desired data. There are various mechanisms and technologies suitable for erasing and programming different types of Flash memories. In this present invention, the well-known Fowler-Nordheim (F-N) tunneling mechanism is described as an example.
A memory array comprises a plurality of memory cells arranged in columns and rows. In each row, the control gates of the cells are connected to form word lines. The source and drains of the cells in a column of cells are connected to form source and bit lines. A cell can be read, erased, and programmed in this array by applying proper bias voltages to the word lines and the bit lines connected to the source and drains.
There are several types of memory arrays found in the prior art. For example, NOR, NAND, AND, DINOR, dual string NOR, and OR type arrays are used. Typically, these memory arrays require the used of an isolation region between adjacent bit lines or sources. Conventionally, shallow trench isolation (STI) is used between bit lines or source lines of Flash cells to reduce disturbances of non-selected cells during erasing or programming of selected cells. The reason such disturbances may occur is because of the relatively large voltages that are applied to the cell bit lines or source lines during the erase and program operations. However, these STI regions typically require large silicon surface areas and reduce array layout efficiency.
Referring now to FIGS. 1a and 1b, diagrams of a prior art, Flash memory are shown. A cross section of the Flash memory cell is shown in FIG. 1a. An AND-type array architecture is shown in FIG. 1b. This Flash memory cross section is disclosed in U.S. Pat. No. 5,793,678 to Kato et al. The memory cells 10A, 10B, and 10C, comprise a floating gate 13 that is typically fabricated using the first level of polysilicon. Control gates 12 typically are fabricated using the second level of polysilicon and are connected across a row of cells in the array to form a word line. The drain regions 16 are typically formed as N-type diffusions and are connected in the array to become a bit line. The source regions 17 are also typically formed as N-type diffusions and are connected in the array to become a source line.
Each cell 10A performs a basic transistor function. However, the threshold voltage for the transistor is determined by the electron charge stored on the floating gate 13 rather than simply the ion implantation dose used during the fabrication process. When a large number of electrons are stored on the floating gate 13, then the threshold voltage of the Flash cell 10A becomes high enough to cause the cell to be in the OFF state even when a reading voltage of, for example, VDD is applied to the control gate. Conversely, if the floating gate 13 is depleted of electrons, then the threshold voltage of the cell 10A is decreased. The cell will be in the ON state when the read voltage is applied. Therefore, the threshold voltage may be used to store and to read out the stored data state.
An oxide layer 15 of typically about 10 nanometers thickness is formed between the floating gate 13 and the substrate 11. This thin oxide layer 15 is typically called the tunnel oxide because it provides an electron tunnel path during erase and program operations. A thick oxide-nitride-oxide (ONO) layer 14, of typically about 15 nanometers thickness, is formed between the floating gate 13 and the control gate 12 to thereby prevent stored electrons from migrating from the floating gate 13 to the control gate 12. Further, the ONO layer 14 provides a good coupling ratio between the control gate and the floating gate. As an important observation, a shallow trench isolation (STI) oxide layer 19 is formed in the spaces between adjacent bit lines 16 and 18 and between adjacent source lines 17 and 20. The presence of the STI regions 19 isolates the different voltages applied to the individual bit lines and source lines of cells during program or erase operations. According to current technology, the STI depth and width are about 0.30 microns and 0.25 microns, respectively. The STI regions occupy about 30 percent of the substrate surface area on a per cell basis.
Referring now to FIG. 1b, a conventional AND-type array associated with the above-described cell structure is shown. In this array, columns of Flash memory cells 31, 33, 35, and 37, have separate bit lines 41, 43, 45, and 47. Each column also has separate source lines 42, 44, 46, and 48. Note that the bit lines and the source lines are physically separated by the STI regions located in columns 32, 34, and 36. The purpose of these STI regions 32, 34, and 36, is to prevent programming voltages applied to either the bit lines or the source lines of a selected cell from coupling onto the bit lines or source lines of unselected cells.
In order to erase and program a Flash memory cell, proper bias voltages must be applied to the control gate 12, the drain 16, and the source 17, of the selected cell 10B. Referring now to FIG. 1c, exemplary bias conditions are shown for the Flash cell of FIG. 1A during an erasing operation. During an erase, the control gates 12 of the selected cells are driven to a large, positive voltage. For example, the control gates may be driven to about +20V while the substrate is grounded and the sources and drains are either grounded or left floating. This high voltage on the control gate 12 will capacitively couple onto the floating gate 13 and will create a large electric field across the tunnel oxide layer 15. When the electric field is large enough to overcome the energy barrier of the tunnel oxide layer 15, then tunnel paths will occur to allow electron charge tunneling through the tunnel oxide layer. Tunnel electrons will migrate to the floating gate 13 and increase the threshold voltage of the selected cell.
Referring now to FIG. 1d, an exemplary bias condition for programming the Flash cell is shown. During programming, the control gates 12 of the selected cells are negatively biased to a high voltage of about 15 V. The drains 16 are positively biased to a high voltage of about +5 V in order to create a high electric field across the tunnel oxide 15. This high electric field induces electron charge flow from the floating gate 13 to the drain 16 through F-N tunneling. Because the control gate is highly biased by negative voltage, the channel of the cell will become OFF state and no current will flow. The source 17 of the cell may be left floating or may be driven to a low voltage of about +2 V to reduce the effect of drain side, high voltage on channel punch through. Typically, both positive and negative high voltages must be generated on-chip using a charge pump circuit in order to provide on-chip re-programmability. Because the program operation is performed in bit-selective fashion, the drains 16 of the non-selected cells connected to the selected bit line are coupled to the ground level rather than +5V. This low, drain bias voltage will not create a sufficiently high electric field to cause electron tunneling. Therefore, the non-selected cells will not be programmed.
It is obvious that a significant drawback of the prior art device is the STI isolation 19 required by the basic cell structure. This STI isolation 19 takes about 30% of the silicon area of the array. In addition, at least two additional process steps are required. First, the shallow trench must be etched in the silicon substrate. Second, an oxide deposition must be performed to fill the trench. These steps significantly increase the manufacturing cost.
In order to reduce the area penalty due to the STI requirements in the conventional AND-type Flash memory array, another prior art, called dual string, NOR-type Flash memory array, is disclosed in U.S. Pat. No. 5,844,270 to Kim et al. FIG. 2a shows a diagram of this prior art in cross section. Unlike the previously-described AND-type array, which separates both the bit line and the source line for each column of cells from its adjacent column of cells, the dual string, NOR-type Flash memory cell only separates the bit line. However, a common source line is shared between adjacent columns. By sharing the source line, the STI area between the source lines is eliminated, and the STI penalty is reduced to about 15% of the array. The reason that the source lines of two adjacent cells can be shared in a dual string, NOR-type array is because the source line can be either floating or positively biased to a low voltage of about 2 V during program operation. This biasing condition allows the source lines of adjacent cells to be shared without worrying about the disturb problem. However, the bit lines of adjacent cells must be separated because the voltage applied to the bit line of a selected cell would cause significant disturbance for a non-selected cell.
There is only one type of bias condition suitable for the dual string, NOR-type array. Referring now to FIG. 2c, the bias condition for an erase operation is illustrated. The control gates 22 of the selected cells are driven to a negative, high voltage of about −15 V. The source is floating and the drain of the selected cells is applied with positive, high voltage of about +5 V to erase the cells to a low threshold voltage state. Referring now to FIG. 2d, the programming operation is illustrated. During programming, the selected word line, bit line, and source line are driven with a positive, high voltage of about +10 V, a positive, middle voltage of about +5 V, and a ground level, respectively. Since the control gate is biased by a positive high voltage, the channel of the selected cell will be strongly turned ON. A large current will flow through the channel region. The current is about 300 μA to 500 μA per cell under this programming condition. This large channel current, plus the middle, high voltage level of about +5 V applied to the drain, will cause impact ionization to occur near the drain side junction. This, in turn, will cause injection into the floating gate 23. This mechanism is known as Channel-Hot-Electron (CHE) injection programming.
The advantage of CHE programming is that it is much faster than F-N programming. For example, CHE programming may only require about 10 μsec while F-N may require about 1 msec. However, the disadvantage is the large programming current. For the non-selected cells, 0 V is applied to the word line and the bit line. Therefore, the non-selected cell channel current will be zero and CHE programming will not occur. However, both CHE and F-N programming apply low voltage to the source lines of both selected and non-selected cells. Therefore, the sources of adjacent cells can be shared without causing program disturbs.
Referring again to FIG. 2a, the dual string, NOR-type array cell is shown in cross section. Flash memory cells 20B and 20C have separated drain regions 27 and 29. These drain regions 27 and 29 are separated by the STI region 29. However, the cells 20A and 20B have a commonly shared source region 26. Cells 20D and 20E have commonly shared source region 30. The shared-source cell structure of the dual string, NOR-type array significantly reduces the area penalty of the STI region 29 when compared to the AND-type array.
Referring now to FIG. 2b, a conventional array is shown for the dual string, NOR-type device. Adjacent columns 31 and 32 share a common source line 42. Similarly, adjacent columns 34 and 35 share common source line 45, and adjacent columns 37 and 38 share common source line 48. Meanwhile, all the adjacent bit lines 41, 43, 44, 46, 47 and 49 are separated from each other by STI regions 33 and 36. By sharing the source lines, the STI between the source lines can be removed and an area reduction of about 15% is realized. However, the higher integration of the dual string, NOR-type array is not complete. The remaining STI area penalty is a distinct disadvantage.